THE 4-BIT SIGNED COMPARATOR
At the top of the page is an interactive circuit that can compare any two 4-bit signed numbers. The circuit is also known as a 2s complement comparator because, strictly speaking, it assumes that the numbers being compared are 2s complement representations. Given any two 4-bit signed numbers X and Y, the circuit is able to differentiate the following relations: whether X = Y, X > Y, or X < Y.
For the most part the circuit is a 4-bit subtractor that uses the operation X – Y as the basis for comparison. The tests are simple enough. If X – Y = 0, then the two numbers must be equal. If X – Y < 0, then X must be less than Y. And if X – Y > 0, then X is greater than Y. Hence, in addition to the 4-bit subtractor, the circuit comprises some additional gates that serve to explicitly indicate the relation between the two numbers.
Using subtraction to compare two binary numbers is not difficult, as long as we look out for two particular conditions: the values of the signed bit (N) and the overflow bit (V). The signed bit is typically the output of the most significant full-adder; it indicates whether the result is positive (0) or negative (1). The overflow bit is the output signal labeled V; it indicates whether the operation results in a number that is too large (V = 1) or not (V = 0). For example, the operation (-7) – (+3) takes two 4-bit signed numbers and returns a 5-bit signed number. In decimal form (-7) – (+3) = (-7) + (-3) = -10; in binary 2s complement form 1001 – 0011 = 1001 + 1101 = 10110.
When X = Y
Determining whether the two operands X and Y are equal is straightforward. If the outputs of all four adders are 0 then the numbers are equal. Therefore, all we need to do is connect the output of the adders to a common 4-input NOR gate. Recall that the output of the NOR gate is true only when all the inputs are false. Hence, when the signal labeled Z is ON then we know the two numbers are equal. (Because we dont have a 4-input NOR gate available, we connect two 2-input OR gates to a 2-input NOR gate to get the same effect).
When X < Y
If X – Y does not result in an overflow (i.e. V = 0), then the output of the most significant adder (i.e. N) serves as the signed bit. If the signed bit is 1 (i.e. N = 1) then X is less than Y. If the operation caused an overflow (i.e. V = 1), however, for X to be less than Y then the output of the most significant adder must be 0 (i.e. N = 0). Therefore, we can expect N V = 1 when X is less than Y.
When X > Y
When X is greater than Y, three details are particular to the result of X – Y. First, the output of at least one of the full-adders will be ON (i.e. the result is non-zero). Second, there will be no overflow (i.e. V is not ON). Third, the output of the most significant adder will be zero (i.e. N = 0). All these three details taken together mean simply that the result of X – Y is positive.
A clever way to describe the case where X > Y is to simply say: it is not X = Y and it is not X < Y. It may seem
a bit funny that we are taking advantage of the fact that there are three mutually exclusive possibilities.
But engineering is about finding simple solutions. We already know X = Y to be Z = 1, and we already
know X < Y to be N V = 1. Therefore, X > Y must be
Hence, the following switching conclusion applies: