SYNCHRONOUS: 4-BIT COUNTER MODULO-16 D FLIPFLOP
by Isai Damier (Let's connect on twitter @isaidamier )

Once we have determined the state transition table of a design problem, the natural next step is to derive the switching expressions for the circuit. Before we do, however, we typically use a shortcut: decide on which type of flipflops to use. The explanation for why this shortcut is useful follows.

First and foremost, you must realize that a counter is a sequential logic circuit; which means the output of the circuit depends not just on the input but also on the past behavior of the circuit. For example, if the present state of our four-bit counter is 1010, then we know that the previous state must have been 1001 and that the next state will be 1011; in fact, from Figure 1 or the interactive circuit above, you should see that if all you know of a counter is the value of the input signals Clk and E, then you have no idea what the next state is going to be.

Now that we have established a counter as a sequencer, the next time-saving observation is to realize that all sequential circuits inevitably comprise flipflops and latches; otherwise sequencers could not store information. And since the set of flipflops and latches is very small (i.e. RS, D, JK, T), we could as well pick which flipflops we wish to use from the outset and design around that type of flipflop. Of course, the choice of flipflop is not so arbitrary when you recall that T flipflops are built with JK flipflops, which are built with D flipflops, which are built with RS flipflops, which in turn are the most basic useful storage elements (this list of relations is not exhaustive, but it is representative). In general, we tend to design with D flipflops. For instance, VHDL, Verilog, and all other major integrated circuit design software use D flipflops to build sequencers. There are many reasons D flipflops are preferred; one is because they simply clock the input signal without changing it (i.e. for all D flipflops, Q = D as time passes). So for example, if Y is the input to and y is the output of a D flipflop, then y will be equal to Y as time passes. You will develop a greater appreciation for this fact as we formulate the Boolean expressions for our four-bit counter.

Having chosen to use D-flipflops to synthesize our four-bit counter, all we really have left to do is find the flipflop input equations. The input equations are actually the equations for the next states W, X, Y, and Z. We refer to them as input equations because W, X, Y, and Z are the inputs to the D flipflops (see Figure 1). These input equations are combinational circuits and so are easy to formulate: each next state variable is a function of E, w, x, y, and z.

For output W:

E = 0		E = 1

Table 2: Karnaugh Map for W

W = wE’ + (wy’ + wx’ + wz’ + w’xyz)E

For output X:

E = 0		E = 1

Table 3: Karnaugh Map for X

X = xE’ + (xy’ + xz’ + x’yz)E

For output Y:

E = 0		E = 1

Table 4: Karnaugh Map for Y

Y = yE’ + (y’z + yz’)E

For output Z:

E = 0		E = 1

Table 5: Karnaugh Map for Z

Z = zE’ + z’E

Rewriting the four input equations together, we get:

W			=		wE’ + (wy’ + wx’ + wz’ + w’xyz)E
X			=		xE’ + (xy’ + xz’ + x’yz)E
Y			=		yE’ + (y’z + yz’)E
Z			=		zE’ + z’E

At first glance there seems to be no pattern but madness in these equations. After rearranging the equations, however, you should see how you can easily extend the techniques you learn here to create counters of any size whatsoever. So let's rearrange the expressions, starting with the least significant bit.

For Z:

	Z	= zE’ + z’E
		= z E

For Y:

	Y	= yE’ + (y’z + yz’)E
		= yE’ + y’zE + yz’E		After expanding the E
		= y(E’ + z’E) + y’zE		After factoring out the y
		= y(E’ + z’) + y’zE		After applying DeMorgan’s		A + A’B = A + B
		= y (zE)’ + y’(zE)		After applying DeMorgan’s		A’ + B’ = (A + B)’
		= y (zE)		After rewriting in XOR form.

For X:

	X	= xE’ + (xy’ + xz’ + x’yz)E
		= xE’ + xy’E + xz’E + x’yzE		After expanding the E
		= x(E’ + y’E + z’E) + x’yzE		After factoring out the x
		= x(E’ + y’ + z’E) + x’yzE		After applying DeMorgan’s to		E’ + y’E = E’ + y’
		= x(E’ + y’ + z’) + x’yzE		After applying DeMorgan’s to		E’ + z’E = E’ + z’
		= x(yzE)’ + x’yzE		After applying DeMorgan’s to		E’ + y’ + z’ = (yzE)’
		= x (zyE)		After rewriting in XOR form.

For W:

	W	= wE’ + (wy’ + wx’ + wz’ + w’xy)E
		= wE’ + wy’E + wx’E + wz’E + w’xyE		After expanding the E
		= w(E’ + y’E + x’E + z’E) + w’xyzE		After factoring out the w
		= w(E’ + y’ + x’E + z’E) + w’xyzE		After applying DeMorgan’s to		E’ + y’E = E’ + y’
		= w(E’ + y’ + x’ + z’E) + w’xyzE		After applying DeMorgan’s to		E’ + x’E = E’ + x’
		= w(E’ + y’ + x’ + z’) + w’xyzE		After applying DeMorgan’s to		E’ + z’E = E’ + z’
		= w(zyxE)’ + w’xyzE		After applying DeMorgan’s to		E’ + y’ + x’ + z’ = (zyxE)’
		= w (zyxE)		After rewriting in XOR form.

So the equations from least significant bit to most significant bit are:

Z		=		z E
Y		=		y (zE)
X		=		x (zyE)
W		=		w (zyxE)

Do you see the pattern yet? If we use D0, D1, D2, D3, …, D_n instead of Z, Y, X, W, …, ETC. as the next state signals, and we use Q0, Q1, Q2, Q3, …, Q_n instead of z, y, x, w, …, etc. as the present state signals; then the pattern for the input equations would be as follows:

D0		=		Q0 EQ0
D1		=		Q1 EQ0
D2		=		Q2 EQ0Q1
D3		=		Q3 EQ0Q1Q2
…
Dn		=		Qn EQ0Q1Q2Q3…Qn-1

At this point we can build the circuit. But before we do, let’s address the influence of time on the operation of the circuit.

At the beginning we said that a counter will run through a predetermined sequence of numbers continuously as long as time exists. What this means in practice is that the essential input to a counter circuit is a clock signal. In other words, a clock signal (Clk) must serve as the driving impetus moving the circuit from state to state. This clock signal is incorporated into the circuit through the clock input of the flipflop: all the flipflops are directly wired to the clock input switch Clk; the clock signal also serves to synchronize the flipflops.

From here on we will assemble the circuit, starting with the least significant bit. We show you the steps so you may follow the practice of testing your work as you build so as to catch errors early in the synthesis process.

Here is the circuit for the least significant bit Z. Notice that this circuit is also a one-bit counter that counts from 0 to 1 (2¹-1) and back again to 0, 1, etc.

Now we add the circuit for Y, turning the circuit into a 2-bit counter that counts from zero to three (2²-1).



We will add the X bit the same way. At this point you should see the pattern and how to extend the counter ad infinitum. This 3-bit counter can count from zero to seven (2³-1).



Do you anticipate what block we will add to create a 4-bit counter? A AND Gate, a XOR Gate, and a D Flipflop! Here is the 4-bit circuit.



Notice that in creating a 4-bit counter, you have incidentally created a 1-bit, 2-bit, and 3-bit counter along the way. What this means is you can connect blocks of counters to build larger counter. For this reason, the final circuit below includes an output carry bit. The carry bit allows designers to chain small counters to build larger counters. For example, a carry bit can be connected into the Enable input of another 4-bit counter to form an 8-bit counter.

I am going to trust you to allow me to show you one final trick. Circuit 5 uses D-latches instead of D-flipflops. Therefore, it is not really the same as the main interactive circuit at the top of the page. Can you guess the difference? For one thing Circuit 5 is cheaper to build, because latches are cheaper than flipflops. But that’s not the main concern. The problem with Circuit 5 is that if the Enable switch flickers OFF and ON while the clock signal is risen (i.e. ON), the counting values will change. That’s not supposed to happen. Therefore, unless you can guarantee that the Enable signal will not change while the clock signal is HIGH, use flipflops instead of latches.