

4BIT MODULO 16 JK BINARY COUNTER

Present State  NEXT STATE  

E = 0  E = 1  
zyxw  ZYXW  ZYXW 
0000  0000  0001 
0001  0001  0010 
0010  0010  0011 
0011  0011  0100 
0100  0100  0101 
0101  0101  0110 
0110  0110  0111 
0111  0111  1000 
1000  1000  1001 
1001  1001  1010 
1010  1010  1011 
1011  1011  1100 
1100  1100  1101 
1101  1101  1110 
1110  1110  1111 
1111  1111  0000 
By simply looking at the counter in the main interactive circuit, you can probably see the pattern by which we build the counter: for each bit we use one JK flipflop and one AND gate. As such, if we wanted to extend our counter from 4–bit to 7bit, we would just add three more flipflops and three more AND gates to the circuit.
From an analysis point of view, the reason this counter works is because JK flipflops toggle when both inputs are asserted (i.e. J=1, K=1). So, for example, on every cycle of the clock the least significant bit W always toggles. The reason the other bits don’t toggle has to do with the AND gates that are in the way. The output of an AND gate is asserted only when all the inputs are asserted. As a consequence for the counter, a bit will only toggle when all the less significant bits that precede it are asserted. Play with the circuit to verify this truth.
Getting the switching expression for this counter can be easy or it can be difficult. Here is the easy non–rigorous derivation.
From the circuit (Figure 1) we can see that both J and K are always connected to the same incoming signals for all the flipflops. This means J and K will always be equal, either to 1 or to 0, but never be different from each other. Therefore, we are interested in cases where the JK flipflops toggle.
Figure 1: JK Counter with labeled AND gates
For the least significant flipflop, whose output is W, it is clear that unless E = 1 no toggling will occur. And so we say
J_{0} = K_{0} = E
For the second least significant flipflop, whose output is X, AND gate #1 is the input of J_{1} and K_{1}. So since the output signal of the AND gate is 1 only when both E and W are 1, we say
J_{1} = K_{1} = E • W.
We follow the same pattern to get the output for J_{2} and K_{2}. AND gate #2, which feeds into J_{2} and K_{2}, is the combination of signal X and signal E • W. And so
J_{2} = K_{2} = (E • W) • X.
For J_{3} and K_{3} we use the output of AND gate #3. Therefore we have
J_{3} = K_{3} = (E • W • X) • Y.
The output of AND gate #4 does not feed into any of the flipflops in our circuit. Instead it serves as the output carry of the counter. The importance of the output carry bit is this: if we had two four–bit counters, for example, and we wanted to connect them to create a larger eight–bit counter; then we would connect the output carry of one of the four–bit counters into the Enable input of the other four–bit counter. The two connected four–bit counters would then behave as an eight–bit counter.
J_{0} = K_{0} = E 
J_{1} = K_{1} = E • Q0 
J_{2} = K_{2} = E • Q0 • Q1 
J_{3} = K_{3} = E • Q0 • Q1 • Q2. 
Figure 2: JK Counter with outputs relabeled
From this pattern you can extend the counter to any number of stages you need.