

THE 4 TO 1 LINE MULTIPLEXER

Data Train/Bus to Y  S1  S0 

D0  0  0 
D1  0  1 
D2  1  0 
D3  1  1 
At face value a multiplexer is a logic circuit whose function is to select one data line from among many. For this reason, many people refer to multiplexers as data selectors. We show the block diagram of a 4x1 multiplexer in Figure 1. The wedge shape of the symbol is not accidental. It is supposed to depict how the multiplexer funnels information from multiple lines to one line. But as in many things in life, the face value is only part of the story. With a little imagination, you can implement any Boolean function with multiplexers. But we are getting ahead of ourselves just a little bit. As a data selector, a multiplexer is still very useful. Registers and counters, for example, often depend on multiplexers to maintain data integrity. Specifically, a universal shift register employs multiplexers for mode selection. In such application each of the data lines represents one mode of operation.
Table 1 below is the truth table of a three input XOR gate. The table is arranged such that X is the most significant bit and Z is the least significant bit. To implement the function using a single 4x1 mux, we begin by assigning the most significant bit in the table to the most significant selector switch: S1 = X. We do the same for the next significant bit until there are no selector switches left: S0 = Y. Next, we treat Z as the data input to the multiplexer; so that X and Y will determine the relationship between Z and F. Here is the end result: when XY = 00, F = Z; when XY = 01, F = Z’; when XY = 10, F = Z’; when XY = 11, F = Z. Table 2 shows the XOR truth table as mapped to the multiplexer.
X  Y  Z  F  

0  0  0  0  
0  0  1  1  
0  1  0  1  
0  1  1  0  
1  0  0  1  
1  0  1  0  
1  1  0  0  
1  1  1  1 
S1  S0  DATA  F  

X  Y  Z  F  
0  0  0  0  
0  0  1  1  
0  1  0  1  
0  1  1  0  
1  0  0  1  
1  0  1  0  
1  1  0  0  
1  1  1  1 
It is customary to assume that the signal Z is available in both true and complemented forms. Nonetheless, we show the inverter in our design in Figure 2.
As shown in Table 3 below, a majority function is a logic circuit whose output is true if more than 50% of the inputs are true. The output is false otherwise.
X  Y  Z  F  

0  0  0  0  
0  0  1  0  
0  1  0  0  
0  1  1  1  
1  0  0  0  
1  0  1  1  
1  1  0  1  
1  1  1  1 
There is no specific rule for choosing the most significant bit when building the truth table from the Boolean expression. However, once you build the table, the significance of the bits must coincide with the significance of the selector switches of the multiplexer. We show the mapping in Table 4.
S1  S0  DATA  F  

X  Y  Z  F  
0  0  0  0  
0  0  1  0  
0  1  0  0  
0  1  1  1  
1  0  0  0  
1  0  1  1  
1  1  0  1  
1  1  1  1 
From a multiplexer’s perspective, it is customary to show the relationship between the output F and the input data lines as a function of the selector switches. We do so in Table 5 below. Table 5 is really just a collapsed version of Table 4. In Table 4 each permutation of S1S0 is repeated twice (i.e. 00, 00; 01, 01; etc). Table 5 shows each permutation once.
S1  S0  F  

X  Y  F  
0  0  0  
0  1  Z  
1  0  Z  
1  1  1 
rom Table 5 (or Table 4) we can see that the value of F does not depend on Z when S1S0 = 00 or S1S0 = 11. Figure 3 below shows the circuit implementation of the majority function.
The procedure we use to implement the two examples with the 4–to–1 multiplexer is straightforward. You can follow the same method to implement any three input function with a 4x1 mux. Indeed the general rule is true: you can implement any n input function with a multiplexer that has n–1 selector switches. The first n–1 inputs are assigned to the selector switches; the last input is treated as the source of data to the multiplexer.