

THE DATA LATCH R/S BASE

TRUTH TABLE  

Input  Output  
C  D  Q  notQ  
1  0  0  1  
1  1  1  0  
0  X  last Q  last notQ 
If you played with the interactive Data Latch circuit at the top of this page, then you saw that the value of the input (D) is reflected in the output (Q) when the clock (Clk) is asserted. In other words, when the clock signal is unasserted the output is locked and cannot be changed; however, when the clock signal is HIGH then the output follows the input. (Note: in this article, we use C and Clk interchangeably for the clock input signal).
The analysis of the Data Latch is as simple as its operation. First we will solve for the switching (Boolean) function using a nice little technique. Then from the Boolean expression we will write the state
transition table and draw the state diagram.
To get the Boolean function, we rename (q) the feedback wire coming from the output Q. We do the same for the feedback wire coming from notQ, renaming it notq. See figure 1 below.
Using the circuit diagram in figure 1, we just solve for the output Q in terms of little q and the inputs D and C. To make things easy for you to see, before we start solving, we also label the output of the inverter X and the intermediate NAND gates T1 and T2, as shown in figure 2 below.
Now we solve: The symbol for the NAND gate is () and the symbol for the NOT gate is the superbar ().
X = D  to get X we take the complement of D  
T1 = D Clk  to get T1 we take the NAND of D and Clk  
T2 = X Clk  to get T2 we take the NAND of X and Clk  
Q = T1 notq  to get Q we take the NAND of T1 and notq  
notQ = T2 q  to get Q we take the NAND of T1 and notq 
Now that we have expressed the outputs of the five gates as algebraic equations, our next job is to combine them to solve for Q in terms of q and the inputs D and Clk.
Q = T1 notq  
Q = T1 notQ  after substituting for  notq = notQ (it's the same wire we split!)  
Q = T1 (T2 q)  after substituting for  notQ = T2 q  
Q = (D Clk) (T2 q)  after substituting for  T1 = D Clk  
Q = (D Clk) ((X Clk) q)  after substituting for  T2 = X Clk  
Q = (D Clk) ((D Clk) q)  after substituting for  X = D 
At this point we are done solving for Q. However, best practice says we should simplify the equation to get a minimal cost expression that defines the circuit; minimal cost means as few gates and as few inputs as possible. If you don't get the simplification process below the first time, don't worry about it. With enough practice you will get there. Here goes:
Q = (D Clk) ((D Clk) q)  
Q = (D • Clk) • (( D • Clk ) • q)  after rewrite each NAND as ANDNOT  
Q = (D • Clk) • ((D • Clk) • q)  after cancelling the double negatives  
Q = (D • Clk) + ((D + Clk) • q)  after substituting for the complements  • = +  
Q = (D • Clk) + ((D + Clk) • q)  after cancelling the double negatives  
Q = (D • Clk) + (D • q + Clk • q)  after expanding the q  
Q = D • Clk + D • q + Clk • q  after cleaning out the parentheses. 
Now we are really done solving for Q. Some textbooks will have the answer as Q = D• Clk+ Clk• q. However, I prefer our answer because our answer expresses a more stable Data Latch circuit. They got their answer using a Kmap. Later, at the end of this article, I will show you how they got theirs. But for now let's proceed to the state transition table.
A state transition table shows how the given state and the input condition of a circuit interact to produce the output of the circuit. As such, the table’s rows are labeled by state and the table’s columns are labeled by input condition. From the Boolean expression we just derived, we can see that the circuit is defined by one state variable q and two input variables D and Clk. Consequently, the state transition table will have two states/rows (q = 0 and q = 1) and four input conditions/columns (D Clk = 00, D Clk = 01, D Clk = 10, D Clk = 11). We show the table in table 1 below, using C for Clk.
Given state q 


Input Condition  
CD=00  CD=01  CD=10  CD=11  
0  
1 
Next, to fill the table, evaluate the equation Q = D • Clk + D • q + Clk • q for Q by substituting the values q, C,
and D. For example, to fill the cell where q = 0 intersect CD = 00, we evaluate Q at those values:
Q  =  D • Clk + D • q + Clk • q  
Q  =  0 • 0 + 0 • 0 + 0 • 0  
Q  =  0 • 0 + 0 • 0 + 1 • 0  
Q  =  0 + 0 + 0  
Q  =  0 
Given state q 


Input Condition  
CD=00  CD=01  CD=10  CD=11  
0  0  
1 
Given state q 


Input Condition  
CD=00  CD=01  CD=10  CD=11  
0  0  0  0  1 
1  1  1  0  1 
Table 3 is pretty easy to understand. However, we are often required to show an even easier to understand representation of the circuit: a state diagram. We will show you the state diagram first; then we will use our words.
Each circle in the state diagram represents a state, as the labels indicate, and the curved arrows represent movement between states resulting from the input conditions.
Our final step in the analysis is to indicate which transitions are unstable. There are two ways to tell where a circuit is unstable: there is an easy way, and then there is an easier way. The easy way is to look
at the state transition table (table 3) and mark as unstable every cell where Q ≠ q. For example, when q = 0, if CD = 11, then Q = 1. Therefore mark that cell as unstable since Q ≠ q. The easier way is to just look
at the state diagram and select as unstable the arrows that show movement from one state to another; the arrows that loop back to the same state are stable.
Okay. Earlier I promised to show you how those textbooks get Q = D • Clk + Clk • q. Here it is. Change the state transition table (table 3) into a Kmap, by just swapping the column where CD = 10 with the column where CD = 11, and then solve the Kmap for a switching function
Given state q 

Input Condition  
CD=00  CD=01  CD=10  CD=11  
0  0  0  0  1 
1  1 
1 
0  1 