THE DATA LATCH R/S BASE
by Isai Damier (Let's connect on twitter @isaidamier )

Introduction

Perhaps the simplest memory device in real applications, the Data Latch is really a Clocked Set-Reset Latch with the inputs R and S tied together through an inverter. There are other designs, but essentially they are all the same. One Data Latch can only store one bit of information: a 0 or a 1. Consequently, you will not likely find a Data Latch in a computer. However, you will find the shift register, which is constituted of a group of Data Latches arranged in series. Other applications of the Data Latch abound. For example, most designers — especially students — design omnifarious sequential logic circuits using Data Latches.

If you played with the interactive Data Latch circuit at the top of this page, then you saw that the value of the input (D) is reflected in the output (Q) when the clock (Clk) is asserted. In other words, when the clock signal is unasserted the output is locked and cannot be changed; however, when the clock signal is HIGH then the output follows the input. (Note: in this article, we use C and Clk interchangeably for the clock input signal).

Boolean Function Derivation

The analysis of the Data Latch is as simple as its operation. First we will solve for the switching (Boolean) function using a nice little technique. Then from the Boolean expression we will write the state transition table and draw the state diagram.

To get the Boolean function, we rename (q) the feedback wire coming from the output Q. We do the same for the feedback wire coming from not-Q, renaming it not-q. See figure 1 below.

Figure 1

Using the circuit diagram in figure 1, we just solve for the output Q in terms of little q and the inputs D and C. To make things easy for you to see, before we start solving, we also label the output of the inverter X and the intermediate NAND gates T1 and T2, as shown in figure 2 below.

Figure 2

Now we solve: The symbol for the NAND gate is () and the symbol for the NOT gate is the super-bar ().

X = D		to get X we take the complement of D
T1 = D Clk		to get T1 we take the NAND of D and Clk
T2 = X Clk		to get T2 we take the NAND of X and Clk
Q = T1 not-q		to get Q we take the NAND of T1 and not-q
not-Q = T2 q		to get Q we take the NAND of T1 and not-q

Now that we have expressed the outputs of the five gates as algebraic equations, our next job is to combine them to solve for Q in terms of q and the inputs D and Clk.

Q = T1 not-q
Q = T1 not-Q		after substituting for		not-q = not-Q (it's the same wire we split!)
Q = T1 (T2 q)		after substituting for		not-Q = T2 q
Q = (D Clk) (T2 q)		after substituting for		T1 = D Clk
Q = (D Clk) ((X Clk) q)		after substituting for		T2 = X Clk
Q = (D Clk) ((D Clk) q)		after substituting for		X = D

At this point we are done solving for Q. However, best practice says we should simplify the equation to get a minimal cost expression that defines the circuit; minimal cost means as few gates and as few inputs as possible. If you don't get the simplification process below the first time, don't worry about it. With enough practice you will get there. Here goes:

Q = (D Clk) ((D Clk) q)
Q = (D • Clk) • (( D • Clk ) • q)		after rewrite each NAND as AND-NOT
Q = (D • Clk) • ((D • Clk) • q)		after cancelling the double negatives
Q = (D • Clk) + ((D + Clk) • q)		after substituting for the complements		• = +
Q = (D • Clk) + ((D + Clk) • q)		after cancelling the double negatives
Q = (D • Clk) + (D • q + Clk • q)		after expanding the q
Q = D • Clk + D • q + Clk • q		after cleaning out the parentheses.

Now we are really done solving for Q. Some textbooks will have the answer as Q = D• Clk+ Clk• q. However, I prefer our answer because our answer expresses a more stable Data Latch circuit. They got their answer using a K-map. Later, at the end of this article, I will show you how they got theirs. But for now let's proceed to the state transition table.