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by Isai Damier (Let's connect on twitter @isaidamier )

The interactive Gated D Latch Nand Base digital logic circuit, with Boolean function and truth table.


The particular design of the interactive Gated Data Latch shown above is implemented with four NAND gates. Because from a transistor perspective NAND gates are the most efficient gates with two or more inputs, this Gated D Latch is more cost effective than its cousins (e.g., The Data Latch R/S Base): it uses fewer transistors and fewer wires to accomplish the same task. Apart from efficacy, this Gated Data Latch is like all Gated Data Latches: it is capable of storing and operating on one bit of information. For this reason, in real applications, Gated Data Latches are often found in large groups such as shift registers and counters. Furthermore, because they are simple to use, Gated Data Latches are the preferred multivibrators in graduate design laboratories around the world and they are used to design elaborate machines.

Input Output
CLK D Q not-Q
0 0 Latch Latch
0 1 Latch latch
1 0 0 1
1 1 1 0

We will analyze this Gated Data Latch for four properties: its switching function; the number of states it can be in; how it transitions from state to state; its stable transitions.

The Switching Function

To obtain a switching (or Boolean) function for our interactive Gated Data Latch above, we simply analyze the circuit. A simple analysis method is to begin by labeling the inputs and the outputs of every NAND gate in the circuit. We accomplish this by labeling every wire in the circuit. Figure 1 below shows the circuit with every wire labeled.

 Gated D Latch Nand base image

Figure 1

Before we proceed, you need to be aware of two details: First, during the analysis we do not ever treat Q and not-Q as complements (two signals are complementary if it is 100% guaranteed that their value will always be opposite of each other; we can't assure that). Second, since the output Q also feeds back into the circuit, we will re-label the feedback signal q and then solve for Q in terms of q. q as an input is referred to as the given condition or the given state of the circuit. Figure 2 below should help clarify these two provisions.

 Gated D Latch Nand base image

Figure 2

Now that we have labeled every wire in the circuit, we will algebraically solve for the output Q in terms of the inputs D and CLK and the given state q. To make the algebra easy on the eye we will use C instead of CLK and we will use nand pic for NAND. We attach a number to each NAND gate just to help you follow along; you do not need to number the gates in your own analysis.

Q = A nand pic not-Q NAND # 1
not-Q = q nand pic B NAND # 2
A = D nand pic C NAND # 3
B = A nand pic C NAND # 4

Next we combine the expressions until we get Q in terms of D, C, and q.

Q = A nand pic not-Q
Q = A nand pic (q nand pic B) after substituting for not-Q = q nand pic B
Q = A nand pic (q nand pic (A nand pic C)) after substituting for B = A nand pic C
Q = (D nand pic C) nand pic (q nand pic ((D nand pic C) nand pic C)) after substituting for A = D nand pic C

At this point we have Q in terms of D, C, and q; hence we could stop here. However, we will simplify the expression to get a more cost effective switching function. We will use the superbar (an overhead bar) for NOT and the dot • for AND.

Q = (D • C) • (q • ((D • C) • C)) after rewriting each NAND as AND-NOT
Q = (D • C) (q • ((D • C) • C )) after cancelling the double negatives
Q = (D • C) + (q • ((D • C) + C)) after substituting for the complements = +
Q = D • C + q • (D • C + C ) after cleaning out some parentheses.
Q = D • C + q • D • C + q • C after expanding q
Q = D • C • (1 + q) + q • C after factoring out D • C
Q = D • C + q • C after substituting (1 + q) = 1

From the switching function Q = D • C + q • C we see that the output Q depends on the state variable q and the two input variables D and C. We call q a state variable because it is an input variable that is not under our direct control. We may directly change the value of D or C by just clicking on a switch, but we cannot directly change the value of q by clicking on a switch.

The State Transition Table

Since in Boolean algebra each variable can have two possible values, 0 or 1, the circuit has two possible states (q = 0; q = 1) and four possible input conditions (CD = 00; CD = 01; CD = 10; CD = 11). And since the final state Q is a function of the inputs and of the initial state variable, we can create a table showing how Q changes based on the values of D, C and q. Such a table, Table 1, is shown below. We call the table a state transition table because it shows the final state Q as a function of the input conditions D and C and the initial state q.

Given state
Input Condition
CD=00 CD=01 CD=10 CD=11

Table 1: Empty State Transition Table

To fill the table we simple evaluate Q at the indicated values for CD and q. For example, at C = 1, D = 0, q = 1:

Q = D • C + q • C = 0 1 + 1 • 1 = 0 + 0 = 0.

Hence, we place Q = 0 in the appropriate cell, as shown in Table 2.

Given state
Input Condition
CD=00 CD=01 CD=10 CD=11
1 0

Table 2: State Transition Table

We complete the evaluation of Q and fill the state transition table as shown in Table 3. Feel free to check that our work is correct.

Given state
Input Condition
CD=00 CD=01 CD=10 CD=11
0 0 0 0 1
1 1 1 0 1

Table 3: State Transition Table

State Transition Diagram

Now that we have a complete state transition table, we can use the information to create a state transition diagram. A state transition diagram is a picture showing how the circuit moves from state to state. Figure 3 below shows our state transition diagram.

 Gated D Latch Nand base image

Figure 3

Stable and Unstable Transitions

At this point all that's left is to identify the stable and unstable transitions. In the state transition diagram, the arrows that point from one oval to another oval represent unstable transitions; the arrows that loop back represent stable states. In the table the unstable transitions are the cells where Q ≠ q. Table 4 below shows the unstable transitions in green.

Given state
Input Condition
CD=00 CD=01 CD=10 CD=11
0 0 0 0 1
1 1 1 0 1

Table 4: State Transition Table