THE GATED RS NAND LATCH
The Gated Set-Reset Latch (also known as a Clocked SR Latch) is merely a Set-Reset Latch with a doorway. And we put a door on a set-reset latch for the same reasons we might put a door on anything else: to control access. With a simple set-reset latch, the input signals are free to come in whenever they want. But if we add a door at the entrance, then we effectively control the entire circuit. As long as the door is closed, we have certitude that no matter what is happening at the input, the state of our circuit cannot be changed. And when we want changes at the input to be reflected in the output, we simply open the door.
The door to our set-reset latch is realized with two NAND gates with one of their inputs tied to a controlling signal (Clk). The NAND gates are effective at locking down the circuit because unless both inputs to a NAND gate are asserted, then the output of the NAND gate will not change. Play with the interactive circuit we provide above, and observe that the output of the NAND gates depend not only on the input signals R and S but also on the control signal Clk. Thus when the clock signal is OFF, nothing S or R does can affect the output of the circuit.
Analysis and Verification
The analysis of the Gated Set-Reset Latch is straightforward. We will first use the circuit diagram to solve for a Boolean function. Then from the Boolean function we will get the state transition table and draw a state diagram. A state transition table is a table that shows how the set-reset latch moves from being in one state to being in another state. A state diagram is a picture that uses circles and arrows to show how the circuit moves from state to state.
The Boolean Function
To solve for the Boolean function, we split the crisscrossed wires from the original circuit diagram into individual inputs and outputs. We keep the outputs as Q and not-Q, but we rename the inputs as lowercase q and not-q. The signals Q and q are not different from each other. We use distinguishing labels only to make the analysis easy. Figure 1 below shows the new look of the circuit.
In addition, we label the remaining wires going out of the controlling NAND gates X1 and X2 to make the analysis easy for you to follow. See figure 2 below.
At this moment we will proceed to solve for Q in terms of the inputs S, R, and Clk and the given state q. First we will solve for X1, X2, Q, and not-Q. Then we will use algebraic substitution to get Q in terms of S,
R, Clk, and q. We have no choice but to solve for Q in terms of q because, as you can see from figure 1, q is one of the inputs to the circuit. We refer to q as the given state of the circuit because it is an input
that we cannot directly control; whereas we can easily control S, R, and Clk by just clicking the switches, the value of q is always given to us by the circuit itself (q is actually what we refer to as the memory of
the circuit). Furthermore, since q and not-q are complements, we don't need both of them in our final answer; q will give use all the information we need. You may use pencil and paper to follow along with
us. To keep the notation easy on your eyes, we use C instead of Clk. Also, the symbol for the NAND gate is .
The next phase is to use algebraic substitution to get Q in terms of the inputs S, R, and C and the given state q.
Presently Q is entirely in terms of the input variables S, R, C and the given state variable q. As such, we are technically done solving for Q. However, we can simplify the expression further to get a minimal cost Boolean function. For your reference, the symbol for the AND gate is the dot and the symbol for the NOT gate is the super-bar ().
This time you can celebrate. We are finally done with solving for Q! Our next course of action is to show the state transition table.
The State Transition Table
To show the state transition table, we simply evaluate Q for all possible combinations of the given state q and the input conditions S, C, R, and then we present the result in a table format. Since this is a Boolean exercise, every variable has two possible values, 0 or 1. In view of that, the Gated Set-Reset Latch has two given states (q = 0; q = 1) and eight input conditions (CSR = 000; CSR = 001; CSR = 010; CSR = 011; CSR = 100; CSR = 101; CSR = 110; CSR = 111). We will list the given states along the rows of the table and the input conditions along the columns; that way we can clearly show the relationship between the given states and the input conditions, and their combined effect on Q. Table 1 below shows the empty state transition table.
As we mentioned earlier, we will fill the table by evaluating Q = S C + R q + C q for each combination of the given state q and the input condition CSR, and we will place the result in the appropriate cell. For example, when q = 0 and CSR = 000, then Q is
Since Q = 0, we put 0 in the appropriate cell as shown in Table 2 below. This example should serve to emphasize that the values inside the state transition table are Q valuations.
We fill the rest of the table for you, as shown in Table 3 below. We welcome you to practice your evaluation skills by checking that our valuations are correct.
Before we proceed to drawing the state diagram, observe the following patterns in the state transition table. First, whenever C = 0 then Q = q, no matter what S and R happen to be. We expected this result because C is the lock to the door. Remember what we told you at the beginning of this article: "As long as the door is closed, we have certitude that no matter what is happening at the input, the state of our circuit cannot be changed." Because of this observation, we can actually rewrite Table 3 as Table 4 below; replacing the first four columns with CSR = 0xx. The xx means that S and R are irrelevant when C is 0. Many textbooks don't address the analysis of asynchronous feedback sequential circuits (think latches and flipflops). And the ones that do will normally not give you table 3; they will give you table 4.
The State Diagram
At this point we can move on to drawing the state diagram from Table 4. We use table 4 instead of Table 3 because it is less work. Feel free to use table 3 if you want; it makes no difference. We show the state diagram in figure 3 below.
Our final stretch is to mark the unstable state transitions. From the state transition diagram in figure 3 the unstable transitions are easy to spot: they are the arrows that leave one given state to go to another. If you want to use the state transition table (table 4 or table 3), the unstable transitions are the ones where, for a given cell, Q ≠ q. For example, the cell where q = 0 and CSR = 110 shows an unstable transition because Q = 1. In table 4 below the unstable transitions are shown in green.