THE MASTER SLAVE D FLIPFLOP
by Isai Damier (Let's connect on twitter @isaidamier )

Introduction to the Master Slave Design

Because latches are so straightforward in their operations, it may be unclear why we would need master-slave counterparts. For example, during the active period of the clock signal (i.e. Clk = 1) the output Q of the data latch is supposed to simply reflect the input signal D. And while the clock signal is not asserted (i.e. Clk = 0), the output Q is supposed to ignore changes in the input D. This is simple enough.

A problem with the latches’ simple design, however, is that latches are too sensitive to input conditions. During a single clock cycle, the state of a latch may experience multiple changes depending on the behavior of the input signal during the period when Clk = 1. While for some applications such sensitivity bears no relevancy or are often beneficial; there are applications where it is necessary that the output of a latch change only once during a single clock cycle. For such systems, the master slave flipflop provides the appropriate depth of defense and reliability.

Ckt 1 below is a packaged version of the Presentation Interactive Circuit above. It is also interactive so play around with it to see that it works exactly as the one above. The first data latch is the master, and it changes state when the clock signal is not asserted (Clk = 0); notice that the master is directly controlled by the input signal D. The second data latch is the slave latch. It changes state only at the rising edge of the clock. When the clock signal is changing from 0 to 1, the output Qs of the slave latch takes the value of the output Q_m of the master latch. Because by the time the slave gate is opened the master latch has already captured a signal and is blocked from receiving further inputs, the output Qs can only change state at most once during a single clock cycle.

Hence by placing two redundant latches in series, we get a reliable D flipflop. This version of the master slave D flipflop is also known as a positive edge triggered D flipflop because the slave output Q_s can only change at the positive edge of the clock.

Analysis and Verification

The analysis of the D Master-Slave Flipflop involves exposing four aspects of the circuit. As with all circuits, we want to know a Boolean function that defines the behavior of the circuit. From the Boolean expression, it will be obvious how many states the circuit can be in. Third, we want to see what input conditions will cause the circuit to move between states. And finally we want to know which states are unstable.

The Boolean Function

Because the D Master-Slave Flipflop is constituted of two D Latches connected in series, getting its Boolean function is as easy as combining two D Latch Boolean expressions. Seeing as the expression for the D Latch is Q = D • C + D • q + C • q, we will distinguish the master latch as Q_m and the slave latch as Q_s. In addition, we account for the NOT gates by inverting the Clock variable C of the master latch.

As evidenced by the Boolean expression we just derived, the master-slave flipflop has two state variables q_m and q_s and two input variables C and D. As such, the flipflop has four states and four different input conditions. We show the resulting state transition table below.

Table 1