Binary Numerals Boolean Algebra
NOT Gate OR Gate AND Gate NOR Gate NAND Gate XOR Gate
NAND - Inverter NAND - The AND Gate NAND - The NOR Gate NAND - The OR Gate NAND - The XOR Gate NOR - The Inverter
NOR - The AND Gate NOR - The NOR Gate NOR - The OR Gate NOR - The XOR Gate MUX - The Inverter MUX - The AND Gate
MUX - The NOR Gate MUX - The OR Gate MUX - The NAND Gate MUX - The XOR Gate
Four Bit Adder-Subtractor 4-bit Signed Comparator BCD Adder 4X4 Multiplier Circuit Half-Adder Full-Adder
Half-Subtractor Full-Subtractor BCD to Excess-3 1 to 2 Decoder 2 to 4 Decoder 2x4 Decoder Enable Input
3 to 8 Decoder 4 Input Priority Encoder 2 to 1 Multiplexer 4 to 1 Line Multiplexer Quadruple 2 to 1 Mux 1 to 4 Demultiplexer
Basic R/S Nor Latch Gated R/S Nand Latch Gated D Latch Nand Base Gated D Latch Nor Base Data Latch RS Base RS Nor Latch with Enable
R/S Nand Latch FlipFlop Hierarchy J K FlipFlop Master Slave D FlipFlop Master Slave JK FlipFlop SR Master Slave FlipFlop
Toggle Flipflop Positve Edge Triggered D FlipFlop
Johnson Counter 4-Bit Counter w/ D-Flipflop 4-Bit Modulo-16 JK Binary Counter Modulo-16 Counter w/ Parallel Loading Parallel Register
JK Shift Register S/R 6-Bit Shift Register 4-Bit Parallel Access Shift Register 4-Bit Universal Shift Register Up Counter w/ Toggle FF
Down Counter w/ Toggle FF Up/Down Counter w/ Toggle FlipFlop Set Reset Parallel Shift Register
Serial Adder Moore FSM: Control Circuit for Automatic Door
Structure: -- -- This program is a structural VHDL design of the 4-bit -- Adder-Subtracter. By structural we mean that the -- circuit is constructed using XOR components and Full -- Adder components -- just like the actual physical -- Adder-Substractor. -- -- Consequently, this VHDL circuit is designed in two -- stages. In stage one we define the XOR entity and then -- the Full Adder entity. Here we present a dataflow -- design of the Full Adder circuit. For the structural -- (RTL) design of the circuit, see the Full Adder page -- on Teahlab.com. -- -- In stage two we build the structure of the -- Adder-Substractor using the components we build in -- stage one. -- -- It is very important to learn structural design (RTL) -- strategies because as your assignments become larger -- and larger, knowledge of register transfer level (RTL) -- design strategies become indispensable.
-- A testbench is a program that defines a set -- of input signals to verify the operation of -- a circuit: in this case, the Gated D Latch. -- -- 1] The testbench takes no inputs and returns -- no outputs. As such the ENTITY declaration -- is empty. -- -- 2] The circuit under verification, here the -- Master-slave D flipflop, is imported into -- the testbench ARCHITECTURE as a component.