Binary Numerals Boolean Algebra
NOT Gate OR Gate AND Gate NOR Gate NAND Gate XOR Gate
NAND - Inverter NAND - The AND Gate NAND - The NOR Gate NAND - The OR Gate NAND - The XOR Gate NOR - The Inverter
NOR - The AND Gate NOR - The NOR Gate NOR - The OR Gate NOR - The XOR Gate MUX - The Inverter MUX - The AND Gate
MUX - The NOR Gate MUX - The OR Gate MUX - The NAND Gate MUX - The XOR Gate
Four Bit Adder-Subtractor 4-bit Signed Comparator BCD Adder 4X4 Multiplier Circuit Half-Adder Full-Adder
Half-Subtractor Full-Subtractor BCD to Excess-3 1 to 2 Decoder 2 to 4 Decoder 2x4 Decoder Enable Input
3 to 8 Decoder 4 Input Priority Encoder 2 to 1 Multiplexer 4 to 1 Line Multiplexer Quadruple 2 to 1 Mux 1 to 4 Demultiplexer
Basic R/S Nor Latch Gated R/S Nand Latch Gated D Latch Nand Base Gated D Latch Nor Base Data Latch RS Base RS Nor Latch with Enable
R/S Nand Latch FlipFlop Hierarchy J K FlipFlop Master Slave D FlipFlop Master Slave JK FlipFlop SR Master Slave FlipFlop
Toggle Flipflop Positve Edge Triggered D FlipFlop
Johnson Counter 4-Bit Counter w/ D-Flipflop 4-Bit Modulo-16 JK Binary Counter Modulo-16 Counter w/ Parallel Loading Parallel Register
JK Shift Register S/R 6-Bit Shift Register 4-Bit Parallel Access Shift Register 4-Bit Universal Shift Register Up Counter w/ Toggle FF
Down Counter w/ Toggle FF Up/Down Counter w/ Toggle FlipFlop Set Reset Parallel Shift Register
Serial Adder Moore FSM: Control Circuit for Automatic Door
Structure: -- -- The Quad 2-to-1 Mux is actually four 2-to-1 -- multiplexers sharing one selection switch. The main -- interactive Quadrupple 2-to-1 Mux on Teahlab.com shows -- the basic gate level design of the circuit. However, -- we are doing things just a little bit differently -- here. We are presenting the structural design of the -- quad circuit, of course. We do so by first defining a -- 2-to-1 Mux entity; then, in stage two of the design, -- we connect the single mux components into a unit of -- four. Where we change things a little bit is at the -- single mux level. We show a dataflow design of the -- single mux. For the structural design of the 2-to-1 -- Mux, visit the 2-to-1 Mux page on Teahlab.com. -- -- The two stage approach we present here is one you will -- likely need to use at work. It is customary to present -- dataflow descriptions of the smaller components in a -- design and then connect those components using RTL -- techniques. -- -- The obvious plus sign here, of course, is that you are -- practicing this vital technique using a very simple -- circuit.
-- A testbench is a program that defines a set -- of input signals to verify the operation of -- a circuit: in this case, the Gated D Latch. -- -- 1] The testbench takes no inputs and returns -- no outputs. As such the ENTITY declaration -- is empty. -- -- 2] The circuit under verification, here the -- Master-slave D flipflop, is imported into -- the testbench ARCHITECTURE as a component.